An electric device technology, for example, a semiconductor device technology has been remarkably developed up to now. In particular, a memory device such as DRAM requiring a high integration degree has been required to have active and passive elements with smaller feature sizes, and the semiconductor device and the process technology have correspondingly reduced the feature sizes.
However, when a channel layer is implemented to have a length of 50 nm or less in a transistor, a short channel effect occurs to make it difficult to implement the device. A doping concentration of the channel layer has been made to be increased to temporarily solve the above problem so far. However, it is required to fundamentally solve the above problem when the feature size is more reduced. Some researches have proposed a Recess Channel Array Transistor (RCAT) in which a channel region below a gate of the transistor is recessed to increase an effective gate length or a Spherical Recess Channel Array Transistor (SRCAT) allowing a threshold voltage to be decreased in comparison with the RCAT. Other researches have proposed a vertical transistor in which a channel between a source and a drain is completely surrounded by a gate. Although the structural change in transistor has been tried to overcome the short channel effect, the manufacturing process thereof is complicated.
Nowadays, in order to overcome the performance degradation due to the reduction in feature size, a transistor structure having a metal channel layer is proposed. By forming the channel layer of the transistor with a metal, a mobility of the charges in the channel layer can be improved, and a leakage current occurring due to the short channel effect can thus be reduced. Accordingly, when more attentions are focused on the transistor structure having the metal channel layer, a research on a method capable of reliably manufacturing the transistor having the metal channel layer is also required.